The present invention relates to the field of integrated circuits and, in particular, to a novel method of forming capacitor structures.
A dynamic random access memory (DRAM) cell typically comprises a charge storage capacitor coupled to an access device such as a Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET). The MOSFET functions to apply or remove charge on the capacitor, thus affecting a logical state defined by the stored charge. The amount of charge stored on the capacitor is determined by the capacitance C=xcex5xcex5oA/d, where xcex5 is the dielectric constant of the capacitor dielectric, xcex5o is the vacuum permittivity, A is the electrode (or storage node) area, and d is the interelectrode spacing. The conditions of DRAM operation, such as operating voltage, leakage rate and refresh rate, will in general mandate that a certain minimum charge be stored by the capacitor.
In the continuing trend to higher memory capacity, the packing density of storage cells must increase, yet each must maintain required capacitance levels. This is a crucial demand of DRAM fabrication technologies if future generations of expanded memory array devices are to be successfully manufactured. Nevertheless, in the trend to higher memory capacity, the packing density of cell capacitors has increased at the expense of available cell area. For example, the area allowed for a single cell in a 64-Mbit DRAM is only about 1.4 xcexcm2. In such limited areas, it is difficult to provide sufficient capacitance using conventional stacked capacitor structures. Yet, design and operational parameters determine the minimum charge required for reliable operation of the memory cell despite decreasing cell area.
Several techniques have been developed to increase the total charge capacity or the capacitance of the cell capacitor without significantly affecting the cell area. For example, new capacitor dielectric materials with high dielectric constants have been introduced to replace conventional dielectric materials such as silicon nitride. This way, thin films of materials having a high dielectric constant, such as Ta2O5 (tantalum pentoxide), Barium Titanate (BT), Strontium Titanate (ST), Lead Zirconium Titanate (PZT), or Bismuth Strontium Titanate (BST), have been increasingly utilized as the cell dielectric material of choice of DRAMs.
Although these materials have a high dielectric constant, typically greater than 300, and low leakage currents, there are some technical difficulties associated with these materials. One problem with incorporating these materials into current DRAM cell designs is their chemical reactivity with the polycrystalline silicon (polysilicon or xe2x80x9cpolyxe2x80x9d) that conventionally forms the capacitor electrode. Capacitors made of polysilicon-PZT/BST sandwiches undergo chemical and physical degradation with thermal processing. During the chemical vapor deposition (CVD) of PZT/BST, oxygen in the ambient tends to oxidize the electrode material. The oxide is undesirable because it has a much lower dielectric constant compared to that of PZT/BST, and adds in series to the capacitance of the PZT/BST, thus drastically lowering the total capacitance of the capacitor. Thus, even a thin native oxide layer present on the electrode results in a large degradation in capacitance.
Another attempt at increasing the cell capacitance has been introducing noble metals, such as platinum, iridium, ruthenium, or gold, as lower electrodes for metal-insulator-metal (MIM) capacitors. Unfortunately, these metals have poor conformal properties and poor step coverage. In addition, these noble metals, particularly platinum, have a high reactivity to silicon. Thus, when elements of the platinum group and their oxides are used as electrode materials, unwanted diffusion and reactions are likely to occur between the electrode material and the material of the underlying conductive plug, which is typically polysilicon. Accordingly, a barrier layer is typically employed between the conductive plug and the lower capacitor electrode.
Capacitor electrodes having textured surface morphology have been also introduced to increase the interfacial area between the dielectric thin film and the adjacent electrode and, therefore, to increase the capacitance. For example, in conventional metal-insulator-polysilicon (MIS) capacitors, hemispherical grain polysilicon (HSG) has been introduced as the material of choice for the lower electrode because the increased surface area of the HSG electrode and of its respective interfacial area is directly proportional to the cell capacitance. However, for a metal-insulator-metal (MIM) capacitor, current technologies make it difficult to confer to a metal film the desired textured surface morphology and shape which is characteristic to a hemispherical grain polysilicon electrode.
Accordingly, there is a need for a method of forming an MIM capacitor having increased capacitance per cell and low leakage, as well as a method of forming a capacitor structure that achieves high storage capacitance without increasing the size of the capacitor.
The present invention provides an MIM capacitor with metal nitride electrodes as well as a method of forming an MIM capacitor with low leakage and high capacitance.
The MIM capacitor with metal nitride electrodes of the present invention comprises a first layer of metal nitride formed as part of a lower electrode over an optional conductive support layer of hemispherical grained polysilicon (HSG). The first metal nitride layer may be a titanium nitride (TiN) layer or a TiBN (boron-doped titanium nitride) layer. Prior to the dielectric formation, the first metal nitride layer may be optionally nitridized or oxidized. A dielectric layer of aluminum oxide (Al2O3), for example, is fabricated over the metal nitride layer. An upper electrode of a second metal nitride layer is formed over the dielectric layer. The second metal nitride layer may be a titanium nitride (TiN) layer or a boron-doped titanium nitride (TiBN) layer.
The present invention also provides a method of forming an MIM capacitor with reduced leakage current and high capacitance. A first layer of metal nitride is formed as part of a lower electrode over an optional conductive support layer of hemispherical grained polysilicon (HSG). The first metal nitride layer may be a titanium nitride (TiN) layer or a TiBN (boron-doped titanium nitride) layer. If titanium nitride (TiN) is employed, the titanium nitride (TiN) layer may be formed by either a deposition technique, for example chemical vapor deposition (CVD), or by atomic layer deposition (ALD). If boron-doped titanium nitride (TiBN) is employed, the boron-doped titanium nitride (TiBN) layer may be formed by a deposition method, for example chemical vapor deposition (CVD). After its formation and prior to the dielectric formation, the first metal nitride layer may be optionally subjected to a nitridization or oxidation process.
A dielectric layer is fabricated over the metal nitride layer and after the optional nitridization or oxidation process. The dielectric layer may be formed by either a deposition technique, for example chemical vapor deposition (CVD), or by an atomic layer deposition (ALD) method.
An upper electrode of a second metal nitride layer is formed over the dielectric layer. The second metal nitride layer may be a titanium nitride (TiN) layer or a boron-doped titanium nitride (TiBN) layer. If titanium nitride (TiN) is employed, the titanium nitride (TiN) layer may be formed by either a deposition technique, for example chemical vapor deposition (CVD), or by atomic layer deposition (ALD). If boron-doped titanium nitride (TiBN) is employed, the boron-doped titanium nitride (TiBN) layer may be formed by a deposition method, for example chemical vapor deposition (CVD).
The foregoing and other advantages and features of the invention will be better understood from the following detailed description of the invention, which is provided in connection with the accompanying drawings.